View LTC3835EDHC-1-PBF_3382803.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3835 1 3835fc typical application features applications description low i q synchronous step-down controller the ltc ? 3835 is a high performance step-down switching regulator controller that drives an all n-channel synchro- nous power mosfet stage. a constant-frequency current mode architecture allows a phase-lockable frequency of up to 650khz. the 80a no-load quiescent current extends operating life in battery powered systems. opti-loop compensa- tion allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3835 features a precision 0.8v reference and a power good output indicator. the 4v to 36v input supply range encompasses a wide range of battery chemistries. the track/ss pin ramps the output voltage during start- up. current foldback limits mosfet heat dissipation during short-circuit conditions. high ef? ciency synchronous step-down converter n wide output voltage range: 0.8v v in 10v n low operating quiescent current: 80a n opti-loop ? compensation minimizes c out n 1% output voltage accuracy n wide v in range: 4v to 36v operation n phase-lockable fixed frequency 140khz to 650khz n dual n-channel mosfet synchronous drive n very low dropout operation: 99% duty cycle n adjustable output voltage soft-start or tracking n output current foldback limiting n power good output voltage monitor n clock output for polyphase ? applications n output overvoltage protection n low shutdown i q : 10a n internal ldo powers gate drive from v in or v out n selectable continuous, pulse-skipping or burst mode ? operation at light loads n small 20-lead tssop or 4mm 5mm qfn package n automotive systems n telecom systems n battery-operated digital devices n distributed dc power systems l , lt, ltc, ltm, burst mode, polyphase and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131. comparison of ltc3835 and ltc3835-1 part # clkout/ phasmd extv cc pgood packages ltc3835 yes yes yes fe20/4 5 qfn ltc3835-1 no no no gn16/3 5 dfn v out 3.3v 5a 150f 0.01f v in 4v to 36v i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 3.3h 0.012 20k 3835 ta01 100pf 330pf 33k 62.5k 4.7f 0.22f tg v in boost sw 10f load current (ma) efficiency (%) power loss (mw) 0.01 0.1 1 10 100 1000 10000 3835 ta01b 0.001 1 10 1000 100 0.1 100000 10000 40 50 60 70 80 30 20 10 0 90 100 power loss efficiency v in = 12v; v out = 3.3v ef? ciency and power loss vs load current
ltc3835 2 3835fc absolute maximum ratings input supply voltage (v in ) ......................... 36v to C0.3v top side driver voltage (boost) ............... 42v to C0.3v switch voltage (sw) ..................................... 36v to C5v intv cc , (boost-sw), clkout, pgood ... 8.5v to C0.3v run, track/ss ......................................... 7v to C0.3v sense + , sense C voltages ........................ 11v to C0.3v pllin/mode, phasmd, plllpf ......... intv cc to C0.3v extv cc ...................................................... 10v to C0.3v i th , v fb voltages ...................................... 2.7v to C0.3v (note 1) fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 clkout plllpf i th tracks/ss v fb sgnd pgnd bg intv cc extv cc phasmd pllin/mode pgood sense + sense C run boost tg sw v in 21 t jmax = 125c, ja = 35c/w exposed pad (pin 21) is sgnd must be soldered to pcb 20 19 18 17 7 8 top view ufd package 20-pin (4mm s 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 i th track/ss v fb sgnd pgnd bg pgood sense + sense ? run boost tg plllpf clkout phasmd pllin/mode intv cc extv cc v in sw 21 t jmax = 125c, ja = 37c/w exposed pad (pin 21) is sgnd must be soldered to pcb pin configuration peak output current <10s (tg,bg) ...........................3a intv cc peak output current ................................. 50ma operating temperature range (note 2).... C40c to 85c junction temperature (note 3) ............................. 125c storage temperature range fe package ........................................ C65c to 150c storage temperature range ufd package ..................................... C65c to 125c lead temperature (fe package, soldering, 10 sec) ... 300c
ltc3835 3 3835fc electrical characteristics symbol parameter conditions min typ max units main control loops v fb regulated feedback voltage (note 4); i th voltage = 1.2v l 0.792 0.800 0.808 v i vfb feedback current (note 4) ?5 ?50 na v reflnreg reference voltage line regulation v in = 4v to 30v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; i th voltage = 1.2v to 0.7v measured in servo loop; i th voltage = 1.2v to 2v l l 0.1 ?0.1 0.5 ?0.5 % % g m transconductance ampli? er g m i th = 1.2v; sink/source 5a (note 4) 1.55 mmho i q input dc supply current sleep mode shutdown (note 5) run = 5v, v fb = 0.83v (no load) v run = 0v 80 10 125 20 a a uvlo undervoltage lockout v in ramping down l 3.5 4 v v ovl feedback overvoltage lockout measured at v fb relative to regulated v fb 81012 % i sense sense pins total source current v sense ? = v sense + = 0v ?660 a df max maximum duty factor in dropout 98 99.4 % i track/ss soft-start charge current v track = 0v 0.75 1.0 1.35 a v run on run pin on threshold v run rising 0.5 0.7 0.9 v v sense(max) maximum current sense threshold v fb = 0.7v, v sense ? = 3.3v v fb = 0.7v, v sense ? = 3.3v l 90 80 100 100 110 115 mv mv tg t r tg t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 50 50 90 90 ns ns bg t r bg t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 40 40 90 80 ns ns the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v run = 5v unless otherwise noted. order information lead free finish tape and reel part marking* package description temperature range ltc3835efe#pbf ltc3835efe#trpbf ltc3835efe 20-lead plastic tssop ?40c to 85c ltc3835ife#pbf ltc3835ife#trpbf ltc3835ife 20-lead plastic tssop ?40c to 85c ltc3835eufd#pbf ltc3835eufd#trpbf 3835 20-pin (4mm 5mm) plastic dfn ?40c to 85c ltc3835iufd#pbf ltc3835iufd#trpbf 3835 20-pin (4mm 5mm) plastic dfn ?40c to 85c lead based finish tape and reel part marking* package description temperature range ltc3835efe ltc3835efe#tr ltc3835efe 20-lead plastic tssop ?40c to 85c ltc3835ife ltc3835ife#tr ltc3835ife 20-lead plastic tssop ?40c to 85c ltc3835eufd ltc3835eufd#tr 3835 20-pin (4mm 5mm) plastic dfn ?40c to 85c ltc3835iufd ltc3835iufd#tr 3835 20-pin (4mm 5mm) plastic dfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ (note 2)
ltc3835 4 3835fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3835e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3835i is guaranteed to meet performance speci? cations over the full C40c to 85c operating temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3835fe: t j = t a + (p d ? 35c/w) ltc3835ufd: t j = t a + (p d ? 37c/w) electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v run = 5v unless otherwise noted. note 4: the ltc3835 is tested in a feedback loop that servos v ith to a speci? ed voltage and measures the resultant v fb . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is speci? ed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). symbol parameter conditions min typ max units tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf 70 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf 70 ns t on(min) minimum on-time (note 7) 180 ns intv cc linear regulator v intvccvin internal v cc voltage 8.5v < v in < 30v, v extvcc = 0v 5 5.25 5.5 v v ldovin intv cc load regulation i cc = 0ma to 20ma, v extvcc = 0v 0.2 1.0 % v intvccext internal v cc voltage v extvcc = 8.5v 7.2 7.5 7.8 v v ldoext intv cc load regulation i cc = 0ma to 20ma, v extvcc = 8.5v 0.2 1.0 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v ldohys extv cc hysteresis 0.2 v oscillator and phase-locked loop f nom nominal frequency v plllpf = no connect 360 400 440 khz f low lowest frequency v plllpf = 0v 220 250 280 khz f high highest frequency v plllpf = intv cc 475 530 580 khz f syncmin minimum synchronizable frequency pllin/mode = external clock; v plllpf = 0v 115 140 khz f syncmax maximum synchronizable frequency pllin/mode = external clock; v plllpf = 2v 650 800 khz i plllpf phase detector output current sinking capability sourcing capability f pllin/mode < f osc f pllin/mode > f osc C5 5 a a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative v fb ramping positive -12 8 C10 10 C8 12 % %
ltc3835 5 3835fc typical performance characteristics ef? ciency and power loss vs output current ef? ciency vs load current ef? ciency vs input voltage load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load soft start-up tracking start-up load current (ma) efficiency (%) power loss (mw) 0.01 0.1 1 10 100 1000 10000 3835 g01 0.001 1 10 1000 100 0.1 10000 40 50 60 70 80 30 20 10 0 90 100 burst mode operation forced continuous mode pulse skipping mode v in = 12v v out = 3.3v load current (ma) efficiency (%) 0.01 0.1 1 10 100 1000 10000 3835 g02 0.001 50 60 70 80 40 90 100 v in = 12v v in = 5v v out = 3.3v input voltage (v) efficiency (%) 51015203040 3835 g03 0 25 35 86 88 90 92 94 84 82 96 98 v out = 3.3v 20s/div v out 100mv/ div ac coupled i l 2a/div 3835 g04 20s/div v out 100mv/div ac coupled i l 2a/div 3835 g05 20s/div v out 100mv/div ac coupled i l 2a/div 3835 g06 4s/div forced contin- uous mode 2a/div burst mode pulse- skipping mode 3835 g07 20ms/div 3835 g08 v out 1v/div 20ms/div 3835 g09 v out2 2v/div (master) v out1 2v/div (slave) figure 11 circuit figure 11 circuit figure 11 circuit figure 11 circuit v out = 3.3v figure 11 circuit v out = 3.3v i load = 300a figure 11 circuit figure 11 circuit figure 11 circuit v out = 3.3v figure 11 circuit v out = 3.3v t a = 25oc, unless otherwise noted.
ltc3835 6 3835fc typical performance characteristics total input supply current vs input voltage extv cc switchover and intv cc voltages vs temperature intv cc line regulation maximum current sense voltage vs i th voltage sense pins total input bias current maximum current sense threshold vs duty cycle foldback current limit quiescent current vs temperature sense pins total input bias current vs i th input voltage (v) 5 350 300 250 200 150 100 50 0 20 30 3835 g10 10 15 25 35 supply current (a) 300a load no load temperature (c) C45 4.0 extv cc and intv cc voltages (v) 4.2 4.6 4.8 5.0 6.0 5.4 C5 35 55 3835 g11 4.4 5.6 5.8 5.2 C25 15 75 95 extv cc falling extv cc rising intv cc input voltage (v) 0 5.00 intv cc voltage (v) 5.05 5.15 5.20 5.25 5.50 5.35 10 20 25 3835 g12 5.10 5.40 5.45 5.30 515 30 35 40 i th pin voltage (v) 0 40 60 100 0.6 1.0 3835 g13 20 0 0.2 0.4 0.8 1.2 1.4 C20 C40 80 current sense threshold (mv) pulse skipping forced continuous burst mode (rising) burst mode (falling) 10% duty cycle v sense common mode voltage (v) 0 C700 input current (a) C600 C400 C300 C200 6789 200 3835 g14 C500 12345 10 C100 0 100 duty cycle (%) 0 current sense threshold (mv) 40 80 120 20 60 100 20 40 60 80 3835 g15 100 10 030507090 feedback voltage (v) 0 0 maximum current sense voltage (v) 20 60 80 100 0.2 0.4 0.5 0.9 3835 g16 40 0.1 0.3 0.6 0.7 0.8 120 track/ss = 1v temperature (c) C45 quiescent current (a) 80 85 90 75 3835 g17 75 70 60 C15 15 45 C30 90 0 30 60 65 100 95 pllin/mode = 0v i th voltage (v) 0 input current (a) 2 4 6 8 12 3835 g18 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 v sense = 3.3v t a = 25oc, unless otherwise noted.
ltc3835 7 3835fc typical performance characteristics track/ss pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature sense pins total input current vs temperature shutdown current vs input voltage oscillator frequency vs temperature undervoltage lockout threshold vs temperature oscillator frequency vs input voltage shutdown current vs temperature temperature (c) C45 track/ss current (a) 1.00 1.05 1.10 75 3835 g19 0.95 0.90 0.80 C15 15 45 C30 90 0 30 60 0.85 1.20 1.15 temperature (c) C45 run pin voltage (v) 0.80 0.85 0.90 75 3835 g20 0.75 0.65 0.50 C15 15 45 C30 90 0 30 60 0.55 0.70 0.60 1.00 0.95 temperature (c) C45 regulated feedback voltage (mv) 800 802 804 75 3835 g21 798 796 792 C15 15 45 C30 90 0 30 60 794 808 806 temperature ( c ) C45 C800 input current (a) C700 C500 C400 C300 200 C100 C15 15 30 90 3835 g22 C600 0 100 C200 C30 0 45 60 75 v out = ov v out = 3.3v v out = 10v input voltage (v) 510 0 input current (a) 10 25 15 25 30 3835 g23 5 20 15 20 35 temperature (c) C45 0 frequency (khz) 100 300 400 500 800 700 C5 35 55 3835 g24 200 600 C25 15 75 95 v plllpf = intv cc v plllpf = float v plllpf = gnd temperature (c) C45 3.2 intv cc voltage (v) 3.3 3.5 3.6 3.7 4.2 3.9 C15 15 30 3835 g25 3.4 4.0 4.1 3.8 C30 0 60 45 75 90 falling rising input voltage (v) 510 frequency (khz) 15 25 30 3835 g26 20 35 392 394 398 400 402 396 404 temperature (c) C45 shutdown current (a) 75 3835 g27 C15 15 45 C30 90 0 30 60 0 2 6 8 10 4 12 t a = 25oc, unless otherwise noted.
ltc3835 8 3835fc pin functions clkout (pin 1/pin 19): open-drain output clock signal available to daisychain other controller ics for additional mosfet driver stages/phases. plllpf (pin 2/pin 20): the phase-locked loops lowpass ? lter is tied to this pin when synchronizing to an external clock. alternatively, tie this pin to gnd, v in or leave ? oating to select 250khz, 530khz or 400khz switching frequency. i th (pin 3/pin 1): error ampli? er outputs and switching regulator compensation points. the current comparator trip point increases with this control voltage. track/ss (pin 4/pin 2): external tracking and soft-start input. the ltc3835 regulates the v fb voltage to the smaller of 0.8v or the voltage on the track/ss pin. a internal 1a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to ? nal regulated output voltage. alternatively, a resistor divider on another voltage supply connected to this pin allows the ltc3835 output to track the other supply during startup. v fb (pin 5/pin 3): receives the remotely sensed feedback volt- age from an external resistive divider across the output. sgnd (pin 6/pin 4): small signal ground. must be routed separately from high current grounds to the common (C) terminals of the input capacitor. pgnd (pin 7/pin 5): driver power ground. connects to the source of bottom (synchronous) n-channel mosfet, anode of the schottky recti? er and the (C) terminal of c in . bg (pin 8/pin 6): high current gate drive for bottom (synchronous) n-channel mosfet. voltage swing at this pin is from ground to intv cc . intv cc (pin 9/pin 7): output of the internal linear low dropout regulator. the driver and control circuit are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7f tantalum or other low esr capacitor. extv cc (pin 10/pin 8): external power input to an internal ldo connected to intv cc . this ldo supplies v cc power, bypass- ing the internal ldo powered from v in whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not exceed 10v on this pin. (fe package/ufd package) v in (pin 11/pin 9): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. sw (pin 12/pin 10): switch node connections to inductor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . tg (pin 13/pin 11): high current gate drive for top n-channel mosfet. these are the outputs of ? oating drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. boost (pin 14/pin 12): bootstrapped supply to the top side floating driver. a capacitor is connected between the boost and sw pins and a schottky diode is tied between the boost and intv cc pins. voltage swing at the boost pin is from intv cc to (v in + intv cc ). run (pin 15/pin 13): digital run control input for controller. forcing this pin below 0.7v shuts down all controller functions, reducing the quiescent current that the ltc3835 draws to approximately 10a. senseC (pin 16/pin 14): the (C) input to the differential current comparator. sense+ (pin 17/pin 15): the (+) input to the differential current comparator. the i th pin voltage and controlled offsets between the senseC and sense+ pins in conjunc- tion with r sense set the current trip threshold. pgood (pin 18/pin 16): open-drain logic output. pgood is pulled to ground when the voltage on the v fb pin is not within 10% of its set point. pllin/mode (pin 19/pin 17): external synchronization input to phase detector and forced continuous control input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg signal to be synchronized with the rising edge of the external clock. in this case, an r-c ? lter must be connected to the plllpf pin. when not synchronizing to an external clock, this input determines how the ltc3835 operates at light loads. pulling this pin below 0.7v selects burst mode operation. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 0.9v and less than intv cc selects pulse-skipping operation.
ltc3835 9 3835fc phasmd (pin 20/pin 18): control input to phase selector which determines the phase relationships between tg and the clkout signal. pin functions (fe package/ufd package) exposed pad (pin 21/pin 21): sgnd. must be soldered to the pcb. functional diagram switch logic + C 4.7v v in v in intv cc -0.5v intv cc 0.8v fc 10k bursten clk + C + C C + C + internal supply r lp c lp pllin/mode extv cc intv cc sgnd + 5.25v/ 7.5v ldo sw shdn sleep 0.4v top boost tg c b c in d d b pgnd bot bg intv cc intv cc v in c out v out 3835 fd r sense r b v fb drop out det bot top on s r q q oscillator phase det plllpf pllin/ mode fc bursten ea 0.88v 0.80v track/ss ov v fb 0.5a 1a 6v r a C + r c track/ss i th c c c c2 c ss 2(v fb ) 0.45v slope comp 6mv + C C + sense C sense + icmp ir b run + C C + phasmd clkout f in + C + C pgood v fb1 0.88v 0.72v l shdn
ltc3835 10 3835fc operation (refer to functional diagram) main control loop the ltc3835 uses a constant-frequency, current mode step-down architecture. during normal operation, the external top mosfet is turned on when the clock sets the rs latch, and is turned off when the main current compara- tor, icmp , resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the i th pin, which is the output of the error ampli? er ea. the error ampli? er compares the output volt- age feedback signal at the v fb pin, (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage. when the load current increases, it causes a slight decrease in v fb relative to the reference, which cause the ea to increase the i th voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5.25v low dropout linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5.25v regulator is turned off and a 7.5v low dropout linear regulator is enabled that supplies intv cc power from extv cc . if extv cc is less than 7.5v (but greater than 4.7v), the 7.5v regulator is in dropout and intv cc is approximately equal to extv cc . when extv cc is greater than 7.5v (up to an absolute maximum rating of 10v), intv cc is regulated to 7.5v. using the extv cc pin allows the intv cc power to be derived from a high ef? ciency external source such as one of the ltc3835 switching regulator outputs. the top mosfet driver is biased from the ? oating bootstrap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge. shutdown and start-up (run and track/ss pins) the ltc3835 can be shut down using the run pin. pulling this pin below 0.7v shuts down the main control loop of the controller. a low disables the controller and most internal circuits, including the intv cc regulator, at which time the ltc3835 draws only 10a of quiescent current. releasing the run pin allows an internal 0.5a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 7v on this pin. the start-up of the output voltage v out is controlled by the voltage on the track/ss pin. when the voltage on the track/ss pin is less than the 0.8v internal reference, the ltc3835 regulates the v fb voltage to the track/ss pin voltage instead of the 0.8v reference. this allows the track/ss pin to be used to program a soft start by connecting an external capacitor from the track/ss pin to sgnd. an internal 1a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v (and beyond), the output voltage v out rises smoothly from zero to its ? nal value. alternatively the track/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see applications information section). when the run pin is pulled low to disable the ltc3835, or when v in drops below its undervoltage lockout threshold of 3.5v, the track/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, the controller is disabled and the external mosfets are held off.
ltc3835 11 3835fc operation (refer to functional diagram) light load current operation (burst mode operation, pulse-skipping, or continuous conduction) (pllin/mode pin) the ltc3835 can be enabled to enter high ef? ciency burst mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/mode pin to a dc voltage below 0.8v (e.g., sgnd). to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 0.8v and less than intv cc C 0.5v. when the ltc3835 is enabled for burst mode operation, the peak current in the inductor is set to approximately one-tenth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the aver- age inductor current is lower than the load current, the error ampli? er ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.4v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the i th pin is then disconnected from the output of the ea and parked at 0.425v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3835 draws to only 80a. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the i th pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when the ltc3835 is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (ri cmp ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative, thus operating in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin, just as in normal operation. in this mode, the ef? ciency at light loads is lower than in burst mode operation. however, continuous operation has the advantages of lower output ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the pllin/mode pin is connected for pulse-skipping mode or clocked by an external clock source to use the phase- locked loop (see frequency selection and phase-locked loop section), the ltc3835 operates in pwm pulse-skipping mode at light loads. in this mode, constant-frequency opera- tion is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current ef? ciency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (plllpf and pllin/mode pins) the selection of switching frequency is a tradeoff between ef? ciency and component size. low frequency opera- tion increases ef? ciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3835s controllers can be selected using the plllpf pin. if the pllin/mode pin is not being driven by an external clock source, the plllpf pin can be ? oated, tied to intv cc , or tied to sgnd to select 400khz, 530khz, or 250khz, respectively. a phase-locked loop (pll) is available on the ltc3835 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. in this case, a series r-c should be connected between the plllpf pin and sgnd to serve as the plls loop ? lter. the ltc3835 phase detector adjusts the voltage on the plllpf pin to align the turn-on of the external top mosfet to the rising edge of the synchronizing signal.
ltc3835 12 3835fc the typical capture range of the ltc3835s phase-locked loop is from approximately 115khz to 800khz, with a guarantee to be between 140khz and 650khz. in other words, the ltc3835s pll is guaranteed to lock to an external clock source whose frequency is between 140khz and 650khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). polyphase applications (clkout and phasmd pins) the ltc3835 features two pins (clkout and phasmd) that allow other controller ics to be daisy-chained with the ltc3835 in polyphase applications. the clock output signal on the clkout pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. the phasmd pin is used to adjust the phase of the clkout signal, as summarized in table 1. the phases are calculated relative to the zero degrees phase being de? ned as the rising edge of the top gate driver output (tg). the clkout pin has an open-drain output device. normally, a 10k to 100k resistor can be connected from this pin to a voltage supply that is less than or equal to 8.5v. table 1 v phasmd clkout phase gnd 90 floating 120 intv cc 180 output overvoltage protection an overvoltage comparator guards against transient over- shoots as well as other more serious conditions that may overvoltage the output. when the v fb pin rises to more than 10% higher than its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the run pin is low (shut down). when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 8.5v. operation (refer to functional diagram)
ltc3835 13 3835fc applications information r sense selection for output current r sense is chosen based on the required output current. the current comparator has a maximum threshold of 100mv/r sense and an input common mode range of sgnd to 10v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, i l . allowing a margin for variations in the ic and external component values yields: r mv i sense max = 8 0 when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. a curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. operating frequency and synchronization the choice of operating frequency, is a trade-off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation requires more inductance for a given amount of ripple current. the internal oscillator of the ltc3835 runs at a nominal 400khz frequency when the plllpf pin is left ? oating and the pllin/mode pin is a dc low or high. pulling the plllpf to intv cc selects 530khz operation; pulling the plllpf to sgnd selects 250khz operation. alternatively, the ltc3835 will phase-lock to a clock signal applied to the pllin/mode pin with a frequency between 140khz and 650khz (see phase-locked loop and frequency synchronization). inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is ef? ciency. a higher frequency generally results in lower ef? ciency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance or frequency and increases with higher v in : i fl v v v l out out in = ? ? ? ? ? ? 1 1 ()( ) ? accepting larger values of i l allows the use of low in- ductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l =0.3(i max ). the maximum i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran- sition to burst mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by r sense . lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high ef? ciency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a ? xed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that
ltc3835 14 3835fc inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for the ltc3835: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (syn- chronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub- logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss speci? cation for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately ? at divided by the speci? ed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve speci? ed v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switc out in = h h duty cycle vv v in out in = ? the mosfet power dissipations at maximum output current are given by: p v v ir v i main out in max ds on in max = () + () + () 2 2 1 () 2 2 11 ? ? ? ? ? ? ()( ) + rc vvv dr miller intvcc thmin th ? ? m min sync in out in max f p vv v ir ? ? ? ? ? ? () = () + () ? 2 1 d ds on () where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current ef? ciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher ef? ciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diode d1 shown in figure 6 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in ef? ciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. applications information
ltc3835 15 3835fc applications information c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c i v vvv in max in out in out required i rms ()( ) [] ? / 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3835, ceramic capacitors can also be used for cin. always consult the manufacturer if there is any question. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the ltc3835 output voltage is set by an external feed- back resistor divider carefully placed across the output, as shown in figure 1. the regulated output voltage is determined by: vv r r out b a =+ ? ? ? ? ? ? 0 8 1 .? to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor and the sw line. sense + and sense C pins the common mode input range of the current comparator is from 0v to 10v. continuous linear operation is provided throughout this range allowing output voltages from 0.8v to 10v. the input stage of the current comparator requires that current either be sourced or sunk from the sense pins depending on the output voltage, as shown in the curve in figure 2. if the output voltage is below 1.5v, current will ? ow out of both sense pins to the main output. in these cases, the output can be easily pre-loaded by the v out resistor divider to compensate for the current comparators negative input bias current. since v fb is servoed to the 0.8v reference voltage, r a in figure 1 should be chosen to be less than 0.8v/i sense , with i sense determined from figure 2 at the speci? ed output voltage. figure 1. setting output voltage ltc3835 v fb v out r b c ff r a 3835 f01 figure 2. sense pins input bias current vs common mode voltage v sense common mode voltage (v) 0 C700 input current (a) C600 C400 C300 C200 6789 200 3835 f02 C500 12345 10 C100 0 100
ltc3835 16 3835fc applications information tracking and soft-start (track/ss pin) the start-up of v out is controlled by the voltage on the track/ss pin. when the voltage on the track/ss pin is less than the internal 0.8v reference, the ltc3835 regulates the v fb pin voltage to the voltage on the track/ss pin instead of 0.8v. the track/ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. figure 3. using the track/ss pin to program soft-start ltc3835 track/ss c ss sgnd 3835 f03 soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure 3. an internal 1a current source charges up the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc3835 will regulate the v fb pin (and hence v out ) according to the voltage on the track/ss pin, allowing v out to rise smoothly from 0v to its ? nal regulated value. the total soft-start time will be approximately: tc v a ss ss = ? . 0 8 1 alternatively, the track/ss pin can be used to track two (or more) supplies during start-up, as shown qualitatively in figures 4a and 4b. to do this, a resistor divider should be connected from the master supply (v x ) to the track/ ss pin of the slave supply (v out ), as shown in figure 5. during start-up v out will track v x according to the ratio set by the resistor divider: v v r r rr rr x out a tracka tracka trackb ab = + + ? for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb time (4a) coincident tracking v x (master) v out (slave) output voltage 3835 f04a v x (master) v out (slave) time 3835 f04b (4b) ratiometric tracking output voltage figure 5. using the track/ss pin for tracking ltc3835 v out v x v fb track/ss 3835 f05 r b r a r tracka r trackb figure 4. two different modes of output voltage tracking
ltc3835 17 3835fc applications information intvcc regulators the ltc3835 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v in supply pin or the extv cc pin, respectively, depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc3835s internal circuitry. the v in ldo regulates the voltage at the intv cc pin to 5.25v and the extv cc ldo regulates it to 7.5v. each of these can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7f tantalum, 10f special polymer, or low esr electrolytic capacitor. a ceramic capacitor with a minimum value of 4.7f can also be used if a 1 resistor is added in series with the capacitor. no matter what type of bulk capacitor is used, an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc3835 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5v v in ldo or the 7.5v extv cc ldo. when the voltage on the extv cc pin is less than 4.7v, the v in ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the ef? ciency considerations section. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc3835 intv cc current is limited to less than 41ma from a 24v supply when in the g package and not using the extv cc supply: t j = 70c + (41ma)(36v)(95c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v. the extv cc ldo attempts to regulate the intv cc voltage to 7.5v, so while extv cc is less than 7.5v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 7.5v up to an absolute maximum of 10v, intv cc is regulated to 7.5v. using the extv cc ldo allows the mosfet driver and control power to be derived from the ltc3835 switching regulator output (4.7v v out 10v) during normal operation and from the v in ldo when the output is out of regulation (e.g., startup, short-circuit). if more cur-rent is required through the extv cc ldo than is speci? ed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 10v to the extv cc pin and make sure than extv cc v in . signi? cant ef? ciency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher ef? ciency). for 4.7v to 10v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (24ma)(5v)(95c/w) = 81c however, for 3.3v and other low voltage outputs, addi- tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.25v regulator resulting in an ef? ciency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest ef? ciency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements.
ltc3835 18 3835fc applications information 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, ef? ciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with the capacitive charge pump shown in figure 6. fault conditions: current limit and current foldback the ltc3835 includes current foldback to help limit load current when the output is shorted to ground. if the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100mv to 30mv. under short-circuit conditions with very low duty cycles, the ltc3835 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple cur- rent is determined by the minimum on-time t on(min) of the ltc3835 (180ns), the input voltage and inductor value: i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i mv r i sc sense lsc = 10 1 2 ? () fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to ? ow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage conditions. the comparator (ov) detects overvoltage faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet. the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the ? nal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the ef? ciency has improved. if there is no change in input current, then there is no change in ef? ciency. figure 6. capacitive charge pump for extv cc extv cc v in tg1 sw bg1 pgnd ltc3835 r sense v out vn2222ll + c out 3835 f06 n-ch n-ch + c in 1f v in l1 bat85 bat85 bat85 0.22f
ltc3835 19 3835fc applications information phase-locked loop and frequency synchronization the ltc3835 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the top mosfet (tg) to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of comple- mentary current sources that charge or discharge the external ? lter network connected to the plllpf pin. the relationship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to pllin/mode, is shown in figure 7 and speci? ed in the electrical characteristics table. note that the ltc3835 can only be synchronized to an external clock whose frequency is within range of the ltc3835s internal vco, which is nominally 115khz to 800khz. this is guaranteed to be between 140khz and 650khz. a simpli? ed block diagram is shown in figure 8. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the ? lter capacitor c lp holds the voltage. the loop ? lter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the ? lter compo- nents c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01f. typically, the external clock (on pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.2v. table 2 summarizes the different states in which the plllpf pin can be used. table 2 plllpf pin pllin/mode pin frequency 0v dc voltage 250khz floating dc voltage 400khz intv cc dc voltage 530khz rc loop filter clock signal phase-locked to external clock figure 7. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock plllpf pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3835 f07 2.5 0 100 300 400 500 900 800 700 200 600 figure 8. phase-locked loop block diagram digital phase/ frequency detector oscillator 2.4v r lp c lp 3835 f08 plllpf external oscillator pllin/ mode
ltc3835 20 3835fc applications information minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3835 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t v v on min out in () () < f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3835 is approximately 180ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 200ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signi? cant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: %ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3835 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current has two components: the ? rst is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control cur- rents; the second is the current drawn from the 3.3v linear regulator output. v in current typically results in a small (< 0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t +q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the vin current required for the driver and control circuits by a factor of (duty cycle)/(ef? ciency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current ? ows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for
ltc3835 21 3835fc applications information a 5v output, or a 4% to 20% loss for a 3.3v output. ef? ciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet, and become signi? cant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% ef? ciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance hav- ing a maximum of 20m to 50m of esr. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load (esr), where esr is the ef- fective series resistance of c out . i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac ? ltered closed loop response test point. the dc step, rise time and settling at this test point truly re? ects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series rc-cc ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the ? ltered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the
ltc3835 22 3835fc applications information most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in = 12v(nominal), v in = 22v(max), v out = 1.8v, i max = 5a, and f = 250khz. the inductance value is chosen ? rst based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the plllpf pin to gnd, generating 250khz operation. the minimum inductance for 30% ripple current is: i v fl v v l out out in = ? ? ? ? ? ? ()( ) ? 1 a 4.7h inductor will produce 23% ripple current and a 3.3h will result in 33%. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.84a, for the 3.3h value. increasing the ripple current will also help ensure that the minimum on-time of 180ns is not violated. the minimum on-time occurs at maxi-mum v in : t v vf v vkhz n on min out in max () () . () == = 1 8 22 250 327 s s the r sense resistor value can be calculated by using the maximum current sense voltage speci? cation with some accommodation for tolerances: r mv a sense ?? 8 0 5 8 4 0 012 . . choosing 1% resistors: r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the top side mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p v v cc main = () + [] 1 8 22 5 1 0 005 50 25 00 2 . (. )( ? )? . 3 35 22 5 2 4 215 1 523 1 2 2 () + () ? ? ? ? ? ? ()( ) + v a pf ? ?. .. 3 300 332 ? ? ? ? ? ? () = khz mw a short-circuit to ground will result in a folded back current of: i mv ns v h a sc = ? ? ? ? ? ? ? = 25 001 1 2 120 22 33 21 . ? () . . with a typical value of r ds(on) and = (0.005/c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p vv v a sync = ()( ) () = 22 1 8 22 2 1 1 125 0 022 100 2 ?. ... m mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. cout is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( i l ) = 0.02(1.67a) = 33mv pCp
ltc3835 23 3835fc applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 9. the figure 10 illustrates the current waveforms present in the various branches of the synchronous regulator operating in the continuous mode. check the following in your layout: 1. is the top n-channel mosfet m1 located within 1cm of c in ? 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. does the ltc3835 v fb pin resistive divider connect to the (+) terminals of c out ? the resistive divider must be con- nected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the ? lter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching node (sw), top gate node (tg), and boost node (boost) away from sensitive small-signal nodes. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3835 and occupy minimum pc trace area. 7. use a modi? ed star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top
ltc3835 24 3835fc applications information mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage. figure 9. ltc3835 recommended printed circuit layout diagram c1 1nf c b d b m2 m1 c in l1 c out v out v in 3835 f09 clkout plllpf i th track/ss v fb sgnd pgnd bg intv cc extv cc phasmd pllin/mode pgood sense + sense C run boost tg sw v in ltc3835efe d1 optional figure 10. branch current waveforms r l1 d1 l1 sw r sense v out c out v in c in r in bold lines indicate high switching current. keep lines to a minimum length. 3835 f10
ltc3835 25 3835fc typical applications high ef? ciency 9.5v, 3a step-down converter v out 9.5v 3a c out 150f 0.01f v in 4v to 36v m1 m2 i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 7.2h 0.012 39.2k 3835 ta02 100pf 560pf 35k 432k 100k 100k 4.7f d b cmdsh-3 c b 0.22f tg v in boost sw c in 10f intv cc high ef? ciency 12v to 1.8v, 2a step-down converter v out 1.8v 2a c out 100f ceramic 0.01f v in 12v m1 m2 i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 l1 3.3h 20m 169k 3835 ta03 100pf 3300pf 2.49k 215k 4.7f d b cmdsh-3 c b 0.22f tg v in boost sw c in 10f 100pf m1, m2: si4840dy l1: toko ds3lc a915ay-3r3m
ltc3835 26 3835fc typical applications high ef? ciency 5v, 5a step-down converter v out 5v 5a c out 150f 0.01f v in 4v to 36v m1 m2 i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 3.3h 0.012 69.8k 3835 ta04 100pf 470pf 10k 365k 4.7f d b cmdsh-3 c b 0.22f tg v in boost sw c in 10f high ef? ciency 1.2v, 5a step-down converter v out 1.2v 5a c out 150f 0.01f v in 4v to 36v m1 m2 i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 2.2h 0.012 10k 118k 3835 ta05 100pf gnd 2.2nf 10k 59k 4.7f d b cmdsh-3 c b 0.22f tg v in boost sw c in 10f intv cc
ltc3835 27 3835fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation cb ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) fe20 (cb) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 o C 8 o 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 p 0.05 0.65 bsc 4.50 p 0.10 6.60 p 0.10 1.05 p 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 4.00 p 0.10 (2 sides) 5.00 p 0.10 (2 sides) pin 1 top mark (note 6) 0.75 p 0.05 0.200 ref 0.00 ? 0.05 1.50 ref 0.40 p 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref r = 0.115 typ pin 1 notch r = 0.20 or c = 0.35 0.25 p 0.05 0.50 bsc (ufd20) qfn 0506 rev b r = 0.05 typ 2.65 p 0.10 3.65 p 0.10 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 2.65 p 0.05 2.50 ref 4.10 p 0.05 5.50 p 0.05 1.50 ref 3.10 p 0.05 4.50 p 0.05 package outline 3.65 p 0.05 0.50 bsc
ltc3835 28 3835fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0508 rev c ? printed in usa related parts typical application part number description comments ltc1628/ ltc1628-pg/ ltc1628-sync 2-phase, dual output synchronous step-down dc/dc controller reduces c in and c out , power good output signal, synchronizable, 3.5v v in 36v, i out up to 20a, 0.8v v out 5 ltc1629/ ltc1629-pg 20a to 200a polyphase synchronous controllers expandable from 2-phase to 12-phase, uses all surface mount components, no heatsink, v in up to 36v ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood lt1709/ lt1709-8 high ef? ciency, 2-phase synchronous step-down switching regulators with 5-bit vid 1.3v v out 3.5v, current mode ensures accurate current sharing, 3.5v v in 36v ltc1735 high ef? ciency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1736 high ef? ciency synchronous controller with 5-bit mobile vid control output fault protection, 24-pin ssop , 3.5v v in 36v ltc1778/ ltc1778-1 no r sense current mode synchronous step-down controllers up to 97% ef? ciency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc3708 dual, 2-phase, dc/dc controller with output tracking current mode, no r sense , up/down tracking, synchronizable ltc3711 no r sense current mode synchronous step-down controller with digital 5-bit interface up to 97% ef? ciency, ideal for pentium ? iii processors, 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3728 dual, 550khz, 2-phase synchronous step-down controller dual 180 phased controllers, v in 3.5v to 35v, 99% duty cycle, 5x5qfn, ssop-28 ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3731 3- to 12-phase step-down synchronous controller 60a to 240a output current, 0.6v v out 6v, 4.5v v in 32v ltc3827/ ltc3827-1 low i q dual synchronous controller 2-phase operation; 115a total no load iq, 4v v in 36v 80a no load i q with one channel on no r sense is a trademark of linear technology corporation. figure 11. high ef? ciency step-down converter v out 3.3v 5a c out 150f 0.01f v in 4v to 36v m1 m2 i th sgnd pllin/mode v fb sense + sense C clkout plllpf run pgood track/ss intv cc extv cc bg pgnd ltc3835 l1 3.3h 0.012 68.1k 3835 ta06 100pf 1200pf 10k 215k m1, m2: si7848dp l1: cdep105-3r2m c out : sanyo 10tpd150m 4.7f d b cmdsh-3 c b 0.22f tg v in boost sw c in 10f 39pf

▲Up To Search▲

Price & Availability of LTC3835EDHC-1-PBF

	To Download LTC3835EDHC-1-PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .